This paper deals with a PCB design method to reduce PMIC’s failure due to ESD. Based on ESD scanning, system CDM and current spreading tests, it turns out that a current path between the PMIC and a PCB ground is the most important factor. It is shown that a certain number of vias are required to keep the impedance of the current path low. Also, it would be possible to design a robust PCB without the use of additional protective element.